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W981616BH 512k 2 banks 16 bits sdram publication release date: february 20 00 - 1 - revision a2 general description W981616BH is a high - speed synchronous dynamic random access memory (sdram), organized as 512k words 2 banks 16 bits. using pipelined architecture and 0.175 m m process technology, W981616BH delivers a data bandwidth of up to 332m byt es per second ( - 5). for different applications the W981616BH is sorted into the following speed grades: - 5, - 6, and ? 7 ( l) . accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or fu ll page when a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981616BH is ideal for ma in memory in high performance applications. features 3.3v 0.3v power supply up to 166 mhz clock frequency 524,288 words x 2 banks x 16 bits organization auto refresh and self refresh cas latency: 2 and 3 burst length: 1, 2, 4, 8, and full page burst read, single write mode byte data controlled by udqm and ldqm auto - precharge and controlled precharge 4k refresh cycles/64 ms interface: lvttl packaged in 50 - pin, 400 mil tsop ii pin configuration 46 47 48 49 50 42 43 44 45 38 39 40 41 v ss 1 2 3 4 5 dq0 6 7 8 9 10 11 12 13 cs nc 24 15 14 19 18 17 16 22 21 20 23 25 v cc dq1 v q ss dq2 dq3 v q cc dq4 dq5 v q ss dq6 dq7 v q cc we cas ras ldqm ba a1 a2 a3 a0 a10 v cc 26 27 28 36 37 32 33 34 35 29 30 31 dq15 dq14 v q ss dq13 dq12 v q cc dq11 dq10 v q ss dq9 dq8 v q cc udqm nc clk cke a9 a6 a5 a4 a7 a8 v ss
W981616BH - 2 - pin description pi n number pin name function description 20 - 24, 27 - 32 a0 - a10 address multiplexed pins for row and column address. row address: a0 - a10. column address: a0 - a7. 19 ba bank select select bank to activate during row address latch time, or bank to read/write dur ing column address latch time. 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 dq0 - dq15 data input/ output multiplexed pins for data input and output. 18 cs chip select disable or enable the command decoder. when command de coder is disabled, new command is ignored and previous operation continues. 17 ras row address strobe command input. when sampled at the rising edge of the clock, ras , cas and we define the operation to be executed. 16 cas column address strobe referred to ras 15 we write enable referred to ras 36, 14 udqm/ ldqm input/output mask the output b uffer is placed at hi - z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. 35 clk clock inputs system clock used to sample inputs on the rising edge of clock. 34 cke clock enable cke controls the clock activation and deactivation. w hen cke is low, power down mode, suspend mode, or self refresh mode is entered. 1, 25 v cc power (+3.3v) power for input buffers and logic circuit inside dram. 26, 50 v ss ground groun d for input buffers and logic circuit inside dram. 7, 13, 38, 44, v cc q power (+3.3v) for i/o buffer separated power from v cc , used for output buffers to improve noise immunity. 4, 10, 41, 47 v ss q ground for i/o buffer separated ground from v ss , used for output buffers to improve noise immunity. 33, 37 nc no connection no connection
W981616BH publication release date: february 2000 - 3 - revision a2 block diagram clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #0 r o w d e c o d e r dq0 dq15 ldqm udqm dq buffer cs ras cas we data control circuit note: the cell array configuration is 2048 * 256 * 16 column decoder sense amplifier cell array bank #1 a0 a9 ba r o w d e c o d e r
W981616BH - 4 - functional descripti on power up and initialization the default power up state of the mode register is unspecified. the following power up a nd initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs during power up, all v cc and v cc q pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "n op" state. the power up voltage must not exceed v cc +0.3v on any of the input pins or v cc supplies. after power up, an initial pause of 200 m s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the d q bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refres h cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras , cas , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command onc e a delay equal to t rsc has elapsed. please refer to the next page for mode register set cycle and operation table. bank activate command the bank activate command must be applied before any read or write operation can be executed. the operation is similar to ras activate in edo dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank - to - bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max.). read and write access modes after a bank has been activated, a read or write cycle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle i s a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, seamle ss data access operation among many different pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle.
W981616BH publication release date: february 2000 - 5 - revision a2 burst read command the burst read command is initiated by applying logic low lev el to cs and cas while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register set s type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode register set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. burst write command the burst write command is initiated by applying logic low level to cs , cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting col umn address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. read interrupted by a read a burst read may be interrupted by another read command. when the previous burst is interrupted, the remaining addresses are overridden by the new read address wi th the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri - stated. a fter that point the write command will have control of the dq bus and dqm masking is no longer needed. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interru pted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. write interrupted by a read a read command will interrupt a burst write operation on the same clock cy cle that the read command is activated. the dqs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from the burst write cycl e will be ignored. burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the bur st stop command during other burst length operations is illegal. the burst
W981616BH - 6 - stop command is defined by having ras and cas high with cs and we low at the rising edge of the clo ck. the data dqs go to a high impedance state after a delay, which is equal to the cas latency in a burst read cycle, interrupted by burst stop. if a burst stop command is issued during a full page burst write operation, then any residu al data from the burst write cycle will be ignored. addressing sequence of sequential mode a column access is performed by increasing the address from the column address, which is input to the device. the disturb address is varied by the burst length as sh own in table 2 . table 2 address sequence of sequential mode data access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no ad dress carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address bust length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
W981616BH publication release date: february 2000 - 7 - revision a2 auto - precharge command if a10 is set to high whe n the read or write command is issued, then the auto - precharge function is entered. during auto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto - precharge can not be interrupted before the entire burst operation is completed. therefore, use of a read, write, or precharge command is prohibited during a read or write cycle with auto - precharge. once the precharge operation has started, the bank cannot be reactivated u ntil the precharge time (t rp ) has been satisfied. issue of auto - precharge command is illegal if the burst is set to full page length. if a10 is high when a write command is issued, the write with auto - precharge function is initiated. the sdram automaticall y enters the precharge operation one clock delay from the last burst write cycle. this delay is referred to as write t dpl . the bank undergoing auto - precharge can not be reactivated until t dpl and t rp are satisfied. this is referred to as t dal , data - in to a ctive delay (t dal = t dpl + t rp ). when using the auto - precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy t ras (min). precharge command the precharge command is used to precharg e or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, and ba, are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). self refresh command the self - refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self - refresh command. once the command is registered, cke must be held low to keep the device in self - refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self - refresh operation to save power. the devi ce will exit self - refresh operation after cke is returned high. any subsequent commands can be issued after t rc from the end of self refresh command. if, during normal operation, auto - refresh cycles are issued in bursts (as opposed to being evenly distribu ted), a burst of 4,096 auto - refresh cycles should be completed just prior to entering and just after exiting the self - refresh mode. power down mode the power down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations; therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device.
W981616BH - 8 - the power down mode is exited by bringing cke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t ces (min) + t ck (min). no operation command the no operation command should be used in cases when the sdram is in an idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don't cares. clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation that was currentl y being executed. there is a one - clock delay between the registration of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringi ng cke high. there is a one - clock cycle delay from when cke returns high to when clock suspend mode is exited.
W981616BH publication release date: february 2000 - 9 - revision a2 table of operating m odes fully synchronous operations are performed to latch the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note 1, 2) command device state cken - 1 cken dqm ba a10 a9 - 0 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with autoprecharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto - refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self - refresh exit idle (s.r) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit active l h x x x x x x x x p ower down mode exit any (power down) l l h h x x x x x x x x h l x h x h x x data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: (1) v = valid, x = don't care, l = low level, h = high level (2) cken signal is input level when commands are provided. (3) these are state of bank designated by ba signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the bu rst cycle, device state is clock suspend mode.
W981616BH - 10 - absolute maximum rat ings parameter symbol rating unit notes input, output voltage v in , v out - 0.3 - 4.6 v 1 power supply voltage v cc , v cc q - 0.3 - 4.6 v 1 operating temperature t opr 0 - 70 c 1 storage temp erature t stg - 55 - 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. recommended dc opera ting conditions (t a = 0 to 70 c) parameter sym. min. typ. max. unit notes power supply voltage v cc 3.0 3.3 3.6 v 2 power supply voltage (for i/o buffer) v cc q 3.0 3.3 3.6 v 2 input high voltage v ih 2.0 - v cc +0.3 v 2 input low voltage v il - 0.3 - 0.8 v 2 note : v ih (max.) = v cc /v cc q +1.2v for pulse width < 5 ns v il (min.) = v ss /v ss q - 1.2v for pulse width < 5 ns capacitance (v cc = 3.3v, t a = 25 c, f = 1mhz) parameter sym. min. max. unit input capacitan ce (a0 to a10, ba, cs , ras , cas , we , udqm, ldqm, cke) c i - 4 pf input capacitance (clk) - 4 pf input/output capacitance (dq0 to dq15) c io - 6.5 pf note: these parameters are periodically sampled and not 100% tested
W981616BH publication release date: february 2000 - 11 - revision a2 dc characteristics (v cc = 3.3v 0.3v, t a = 0 ~70 c) parameter sym . - 5 max. - 6 max. - 7 max. - 7l max. unit notes operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i cc1 100 90 80 80 3 standby current t ck = min., cs = v ih v ih /l = v ih (min.) /v il (max.) bank: inactive state cke = v ih i cc2 45 35 30 30 3 cke = v il (power down mode) i cc2p 1 1 1 1 3 standby current clk = v il , cs = v ih v ih /l = v ih (min.) /v il (max.) bank: inactive state cke = v ih i cc2s 8 8 8 8 cke = v il (power down mode) i cc2p s 1 1 1 1 ma no operating current t ck = min., cs = v ih (min.) bank: active state (2 banks) cke = v ih i cc3 5 5 50 45 45 cke = v il (power down mode) i cc3p 3 3 3 3 burst operating current ( t ck = min.) read/ write command cycling i cc4 190 165 145 145 3, 4 auto refresh current ( t ck = min.) auto refresh command cycling i cc5 125 120 110 110 3 self refresh current (cke = 0.2v) self refresh mode i cc6 1 1 1 0.45 parameter sym. min. max. unit notes input leakage current (0v v in v cc , all other pins not under test = 0v) i i(l) - 5 5 m a output leakage current (o utput disable , 0v v out v cc q ) i o(l) - 5 5 m a lvttl outputt 2 h 2 level voltage (i out = - 2 ma) v oh 2.4 - v lvttl output 2 l 2 level voltage (i out = 2 ma) v ol - 0.4 v
W981616BH - 12 - ac characteristics (v cc = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c, notes: 5, 6, 7, 8) parameter sym. - 5 - 6 - 7(l) unit min. max. min. max. min. max. ref/active to ref/active command period t rc 54 70 72 ns active to precharge command period t ras 40 100000 48 100000 48 100000 active to read/write command delay time t rcd 14 20 20 read/write(a) to read/write(b)command period t ccd 1 1 1 cycle precharge to active(b) command period t rp 14 20 20 ns active(a) to active(b) command period t rpd 10 14 16 write recovery time cl* = 2 t wr 7 8 10 cl* = 3 5 6 7 clk cyc le time cl* = 2 t ck 7 1000 8 1000 10 1000 cl* = 3 5 1000 6 1000 7 1000 clk high level width t ch 2 2 2 clk low level width t cl 2 2 2 access time from clk cl* = 2 t ac 4.5 5.5 5.5 cl* = 3 4.5 5 5 output data hold time t oh 2.75 2 .75 3 output data high impedance time t hz 2.75 5 2.75 6 3 7 output data low impedance time t lz 0 0 0 power down mode entry time t sb 0 5 0 6 0 7 transition time of clk (rise and fall) t t 0.5 10 0.5 10 0.5 10 data - in - set - up time t ds 1.5 1.5 1.5 data - in hold time t dh 1 1 1 address set - up time t as 1.5 1.5 1.5 address hold time t ah 1 1 1 cke set - up time t cks 1.5 1.5 1.5 cke hold time t ckh 1 1 1 command set - up time t cms 1.5 1.5 1.5 command hold time t cmh 1 1 1 refresh time t ref 64 64 64 ms mode register set cycle time t rsc 10 12 14 ns (l):for low power
W981616BH publication release date: february 2000 - 13 - revision a2 notes: 1. operation exceeds "absolute maximum rating" may cause permanent damage to the devices. 2. all voltages are referenced to v ss 3. these parameters depe nd on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence is further described in the "functional description" section. 6. ac test conditions. parameter conditions output reference level 1.4v/1.4v output load see diagram below input signal levels 2.4v/0.4v transition time (rise and fall) of input signal 2 ns input reference level 1.4 v 50 ohms 1.4 v z = 50 ohms output ac test load 30pf 7. transition times are measured between v ih and v il . 8. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
W981616BH - 14 - timing waveforms command input timing t ck clk a0-a10 ba v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah
W981616BH publication release date: february 2000 - 15 - revision a2 read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a10 ba dq valid data-out valid data-out
W981616BH - 16 - control timing of input/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz open t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0 -15 (word mask) (clock mask) clk cke dq0 -15 clk input data output data (output enable) (clock mask) dqm dq0 -15 cke clk dq0 -15
W981616BH publication release date: february 2000 - 17 - revision a2 mode reqister set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 ba "0" "0" a3 addressing mode a0 0 sequential a0 1 interleave a9 single write mode 0 burst read and burst write 1 burst read and single write a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 burst length a0 sequential a0 interleave 1 1 2 2 4 4 a0 8 8 reserved reserved a0 full page cas latency reserved a0 reserved 2 3 reserved a0 a6 a5 a4 a0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a10 ba register set data next command a0 reserved "0" "0"
W981616BH - 18 - interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 ba we cas ras cs t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 bank #1
W981616BH publication release date: february 2000 - 19 - revision a2 interleaved bank read (burst length = 4, cas latency = 3, autoprecharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9 a10 ba we cas ras cs t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 bank #1 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz rbb
W981616BH - 20 - interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs ba active read precharge active read precharge active t ac t ac read precharge t ac bank #0 bank #1
W981616BH publication release date: february 2000 - 21 - revision a2 interleaved bank read (burst length = 8, cas latency = 3, autoprecharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t ras t rp t ras t ras t rp t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a0-a9 a10 ba we cas ras cs bank #0 bank #1 read ap* ap*
W981616BH - 22 - interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9 a10 we cas ras cs ba bank #0 bank #1 t ras
W981616BH publication release date: february 2000 - 23 - revision a2 interleaved bank write (burst length = 8, autoprecharge) bank #0 bank #1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rab ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 we cas ras cs active write write active ap* active write ap* ba
W981616BH - 24 - page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t rp t ras t rp t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 we cas ras cs ba active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 bank #1 ap*
W981616BH publication release date: february 2000 - 25 - revision a2 page mode read/wr ite (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 q q q q q q d d d d d (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs ba active read write precharge t ac bank #0 bank #1
W981616BH - 26 - autoprecharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 ba we cas ras cs t rc t rc t ras t rp t ras t rp t rcd t rcd t ac t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 * ap is the internal precharge start timing bank #0 bank #1
W981616BH publication release date: february 2000 - 27 - revision a2 autoprecharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9, a11 a10 bs1 we cs bs0 t rc t rc t ras t rp t ras t rp raa t rcd t rcd rab rac raa caw rab cax rac aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ras cas
W981616BH - 28 - autorefresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9 a10 we cas ras cs ba
W981616BH publication release date: february 2000 - 29 - revision a2 selfrefresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 ba we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t rc no operation cycle
W981616BH - 30 - bust read and single write (burst lenght = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we ba a10 a0-a9 dqm cke dq (clk = 100 mhz) t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 q q q q d d d q q q q t ac t ac read read single write active bank #0 bank #1
W981616BH publication release date: february 2000 - 31 - revision a2 powerdown mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the powerdown mode. when cke goes high, command input must be no operation at next clk rising edge. clk dq cke dqm a0-a9 a10 ba we cs read ras cas
W981616BH - 32 - autoprecharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
W981616BH publication release date: february 2000 - 33 - revision a2 autoprecharge timing (write cycle) 0 11 10 9 8 7 6 5 4 3 2 1 act ap ap ap write act ap d0 d0 d0 ap act d1 ap act d1 d2 d3 ap act write write write d0 d0 d1 d2 d3 d4 d5 d6 d7 ap act d1 d0 act d1 d2 d3 act d0 d1 d2 d3 d4 d5 d6 d7 write write write write d0 (1) cas latency = 2 (2) cas latency = 3 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras (min) . represents the write with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
W981616BH - 34 - timing chart of wri te - to - read cycle in the case of burst length = 4 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read write write d0 d1 dq dq ( a ) command ( b ) command dqm dqm (2) cas latency = 3 q0 q1 q2 q3 d0 read write read write q0 q1 q2 q3 q0 q1 q2 q3 ( a ) command dq dq dqm ( b ) command dqm (1) cas latency = 2 d0 d0 d1 timing chart of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq dq q0 q1 q2 q3 q0 q1 q2 q3 read bst ( a ) cas latency =2 command ( b ) cas latency = 3 command (3) read cycle q4 q4 dq d0 d1 d2 d3 write bst command (2) write cycle d4 note: represents the burst stop command bst
W981616BH publication release date: february 2000 - 35 - revision a2 timing chart of burst stop cycle (prechare command) (in the case of burst length = 8) note: represents the precharge command prcg read prcg 0 11 10 9 8 7 6 5 4 3 2 1 q0 q1 q2 q3 q0 q1 q2 q3 read prcg q4 q4 ( a ) cas latency = 2 ( b ) cas latency = 3 dq dq (1) read cycle (2) write cycle commad commad write prcg d0 d1 d2 d3 d0 d1 d2 d3 write prcg d4 d4 ( b ) cas latency = 3 dq ( a ) cas latency = 2 dqm dqm dq t wr t wr commad commad
W981616BH - 36 - c ke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk cycle no. external internal cke dqm dq clk clk
W981616BH publication release date: february 2000 - 37 - revision a2 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dq m dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dq m dq q5 q4 ( 3 ) q4 clk clk clk
W981616BH - 38 - self refresh/power down mode exit timing asynchronous control input buffer turn on time ( power down mode exit time ) is specified by t cks (min) + t ck (min) command nop clk cke command a ) t ck < t cks (min)+t ck (min) input buffer enable command clk cke command b) t ck >= t cks (min) + t ck (min) input buffer enable note: command nop all input buffer(include clk buffer) are turned off in the power down mode and self refresh mode represents the no-operation command represents one command t ck t ck t cks (min) +t ck (min) t cks (min) +t ck (min)
W981616BH publication release date: february 2000 - 39 - revision a2 package dimensions 50l - tsop (ii) 400 mill seating plane d a2 a1 a e b zd 1 25 50 26 e h e l c l1 q zd 0.88 0.031 0.035 0.002 0.012 max. min. nom. a2 b a a1 0.30 0.90 1.00 0.05 1.10 0.45 1.20 0.15 sym. dimension (mm) max. min. nom. e 0.80 0.031 0.016 l 0.40 0.50 0.60 0.020 0.024 0.395 e 10.03 10.16 10.29 0.400 0.405 0.820 d 20.95 20.82 21.08 0.825 0.830 0.039 0.043 0.018 0.047 0.006 dimension (inch) 0.10 0.004 l1 0.80 0.031 0.004 c 0.20 0.10 0.008 0.15 0.006 0.455 11.76 11.56 11.96 0.463 0.471 h e y q q 0.10 0 o 10 o 0 o 10 o 0.004 controlling dimension: millimeters y
W981616BH - 40 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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